A three-dimensional integrated circuit (3D IC) is manufactured by stacking silicon wafers or dies and interconnecting them vertically. Typically, the interconnections are achieved with through-silicon vias (TSVs) or wires. The stacked dies act as a single device with an improved performance at a lower cost in terms of power consumption and physical footprint compared to chips manufactured employing conventional two-dimensional processes.
The patents studied in this report cover the range of 3D IC and packaging technologies. Some of the insights from the report are produced below:
- The published patent applications in 3D IC have shown a steady growth, especially post 2009.
- The US leads as the jurisdiction with the largest number of published patent applications. However, the quartet of China-Japan-Taiwan-Korea account for close to half of all the published applications in this area. If the current growth trends hold, this group will lead in the years to come as well.
- Most of the leading patent holders have followed the policy of filing in the U.S. in addition to their home countries, clearly indicating the importance of U.S. as a market for them.
